Project

Reverse Dependencies for rggen-core

The projects listed here declare rggen-core as a runtime or development dependency

0.15
A long-lived project that still receives updates
RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
2019
2020
2021
2022
2023
2024